This specification relates to a forced stack device, and more particularly to trading off gate delay versus leakage current by adjusting device widths of such a forced stack device.
Metal oxide semiconductor (MOS) device technologies may scale the MOS transistors to increasingly smaller dimensions. This may result in better device performance. The ability to improve performance while decreasing power consumption has made MOS architecture a dominant technology for integrated circuits.
The choice of power supply (VCC) and threshold voltage (VT) may be important in determining whether the performance of deep sub-micron (e.g. 0.1 xcexcm) transistors may continue to be scaled. However, lower transistor threshold voltages may lead to significant increases in leakage current due to the exponential nature of sub-threshold conductance. For example, about 80 to 90 mV reduction in the threshold voltage may result in about ten-fold increase in the leakage current. Higher leakage currents increase power dissipation that is undesirable for many semiconductor circuit applications. Higher leakage currents may be particularly problematic for mobile and handheld applications, for example.
One approach to addressing this issue has been to use a dual threshold voltage technique. In a dual threshold voltage approach, certain devices on an integrated circuit are configured to have a lower threshold voltage, while other devices on the same integrated circuit may be configured to have a higher threshold voltage. In this manner, devices that cannot tolerate the higher leakage current characteristic of lower threshold voltages may be selected to have higher threshold voltages. Typically only about 10 to 30% of the devices are performance critical and need this lower threshold voltage.
The leakage current reduction provided by this approach, however, is limited. This is because the lower threshold devices still exhibit the higher leakage current characteristic of such devices.